Systemyde International Corporation
		Resume of Monte J. Dalrymple Education: BSEE (with highest honors) 1977, University of California, Berkeley MSEE 1981 (advanced to candidacy 1978) University of California, Berkeley Experience: Systemyde International Corporation 1995-present. Founder of company. YRISC: Designer of implementation of RISC-V ISA. 32-bit or 16-bit bus. SHA-3: Architect/designer of module implementing FIPS PUB 202. SHA-512: Architect/designer of module implementing 512-bit cases of FIPS PUB 180-4. SHA-256: Architect/designer of module implementing 256-bit cases of FIPS PUB 180-4. ISO7816 UART: Architect/designer of module implementing ISO7816 UART. YVR: Designer of implementation of the AVR instruction set. Y51: Designer of 2-clock implementation of the 8051 instruction set. 41CL: Architect/designer of replacement processor board for an HP-41 calculator. Board contains my enhanced clone of the original custom CPU in a MicroSemi FPGA. HDLC: Designer of dual-channel HDLC controller, targeted at a MicroSemi A3P060 FPGA. Y80: Architect/designer of high-performance implementation of the Z80 instruction set. This design and design process was documented in my book "Microprocessor Design Using Verilog HDL." Y90: Architect/designer of high-performance implementation of the Z80/Z180 instruction set, which also includes the full Z180 peripheral set, along with special features for use with an RTOS (paged MMU, robust WDT, and integrated time-slicer). Rabbit 6000: Lead designer of fifth-generation microprocessor. (CPU enhanced with 32-bit instructions, cycle-steal DMA controller, integrated dynamic RAM controller for the on-chip DRAM. Rabbit 5000: Lead designer of fourth-generation microprocessor. (CPU enhanced with a true 16-bit bus, flyby DMA controller, 10/100BASE-T, and 802.11 b/g). The 10/100 and WiFi were externally-supplied IP. Y180-S: Designer of special clone of the Z180 CPU. (Safe-state version for space applications, currently flying on the Juno mission to Jupiter). Rabbit I/O: Designer of multi-function I/O chip. (Counting, timing, PWM, Quadrature decode). Rabbit 4000: Designer of third-generation microprocessor. (CPU enhanced to 32 bits internally, optional 16-bit external bus, integrated DMA controller, and 10BASE-T network port). Y8002: Designer of synthesizable clone of the Zilog Z8002 16-bit microprocessor. Rabbit 3000: Designer of second-generation microprocessor (Enhanced CPU plus expanded complement of peripherals). Z80-SIO: Designer of synthesizable version of the Z80-SIO. Rabbit 2000: Designer of enhanced Z180 microprocessor (CPU plus full complement of peripherals). DMA: Architect/designer of 32-bit DMA controller for an FPGA vendor. UART: Designer of 8250/16450 compatible UART for an FPGA vendor. Y180: Designer of synthesizable clone of the Z180 microprocessor (CPU only). Zilog, Inc. 1978-1995. Held positions as a Design Engineer, Senior Engineer, Staff Engineer, Senior Staff Engineer, Project Leader, Fellow, Director of Architecture, and Senior Technology Fellow. Supervised from one to twenty-five engineers and layout designers at different times, working on these projects: Z89300: Consulting engineer for this family of television controllers. These devices contain an embedded DSP and control all aspects of TV operation. Z87001: Consulting engineer for this single-chip spread-spectrum telephone chip. This device contains an embedded DSP to control all aspects of the telephone operation. Z380: Architect and a designer of this microprocessor, a 16/32 bit upgrade of the original Z80 microprocessor. Z86C93: Designer of the search engine for this Hard Disk controller. The search engine manages the cache on the hard disk controller. Z16C32: Architect and a designer of the IUSC. This 10Mbit/sec serial controller contains an intelligent DMA to manage the data transfer. Z16C35: Architect and designer of the ISCC. This chip joins the Z85C30 SCC with a DMA controller. Z85C80: Designer of this combination of the Z85C30 SCC and a SCSI controller. Z16C30: Architect and a designer of the USC. An advanced 10MBit/sec multi- protocol serial controller. Z85C30: Contributed to the CMOS conversion of this device by an outside design house. Z280: Contributed to the design of this microprocessor. I designed the UART, memory control, cache control, and refresh control, and debugged the execution unit. Z8003: Contributed to the design of this microprocessor. I was primarily responsible for the simulation of the device, using an in-house simulator. Z8015: Verified the logic design of this Memory Management Unit. This predated simulators and was done entirely by hand. Z8530: Designer of this Serial Communications Controller. I designed the device, did most of the layout, wrote the tech manual and the test programs. Skills: Experienced Verilog HDL user. Experienced Synopsys synthesis tool user. Altera, Lattice, MicroSemi and Xilinx FPGA Design tools. C, BASIC and assembly language for Z80/Z180, Z8000 and Rabbit microprocessors. Familiar with most serial protocols, at least at the bit level. Amateur Extra amateur radio license (KR6DC). GMDSS Maintainer commercial radio license (DM00000647). Professional Associations: Senior Member IEEE; Member Phi Beta Kappa, Tau Beta Pi and Eta Kappa Nu. Patents and Publications: 17 U.S. patents granted. Comparing FPGA Technologies, Circuit Cellar, December 2015 Secure Hash Standard, Circuit Cellar, September 2015 Microprocessor Design Using Verilog HDL, ISBN 978-0-9630133-5-4, 2012 Calculator Brain Transplant, Circuit Cellar, October 2010 Advanced Encryption Standard, Circuit Cellar, February 2010 The Evolution of Rabbits, Circuit Cellar, December 2009 Robotics Made Easy, Circuit Cellar, March 2008 Designing for Hostile Environments, Circuit Cellar, January 2008 Cyclic Redundancy Check, Circuit Cellar, August 2006 Third Generation Rabbit, Circuit Cellar, January 2006 Rolling Your Own Microprocessor: Part 2, Circuit Cellar, October 1999 Rolling Your Own Microprocessor: Part 1, Circuit Cellar, September 1999 Updating a Classic: the Z80380 Microprocessor, Circuit Cellar, February 1996 Towards a Serial Communications Subsystem: the Z-SCC, COMPCON 1980
01/27/2016		© Copyright 2016, Systemyde International Corporation