Resume of Monte
J. Dalrymple |
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Education: |
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BSEE (with highest honors) 1977, University of California,
Berkeley |
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MSEE 1981 (advanced to candidacy 1978) University of
California, Berkeley |
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Experience: |
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Systemyde International Corporation 1995-present.
Founder of company. |
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Y8001: |
Designer of synthesizable clone of the Zilog Z8001 16-bit
microprocessor. |
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YRV: |
Designer of implementation of RISC-V ISA. 32-bit or 16-bit bus. |
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SHA-3: |
Architect/designer of module implementing FIPS PUB 202. |
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SHA-512: |
Architect/designer of module implementing 512-bit cases of FIPS PUB 180-4. |
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SHA-256: |
Architect/designer of module implementing 256-bit cases of FIPS PUB 180-4. |
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ISO7816 UART: |
Architect/designer of module implementing ISO7816 UART. |
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YVR: |
Designer of implementation of the AVR instruction set. |
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Y51: |
Designer of 2-clock implementation of the 8051 instruction set. |
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41CL: |
Architect/designer of replacement processor board for an HP-41 calculator.
Board contains my enhanced clone of the original custom CPU in a MicroSemi FPGA. |
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HDLC: |
Designer of dual-channel HDLC controller, targeted at a MicroSemi A3P060 FPGA. |
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Y80: |
Architect/designer of high-performance implementation of the Z80 instruction set.
This design and design process was documented in my book "Microprocessor Design Using Verilog HDL." |
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Y90: |
Architect/designer of high-performance implementation of the Z80/Z180 instruction set,
which also includes the full Z180 peripheral set, along with special features for use with an RTOS
(paged MMU, robust WDT, and integrated time-slicer). |
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Rabbit 6000: |
Lead designer of fifth-generation microprocessor. (CPU enhanced with 32-bit
instructions, cycle-steal DMA controller, integrated dynamic RAM controller for the on-chip DRAM. |
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Rabbit 5000: |
Lead designer of fourth-generation microprocessor. (CPU enhanced with a
true 16-bit bus, flyby DMA controller, 10/100BASE-T, and 802.11 b/g). The 10/100 and WiFi
were externally-supplied IP. |
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Y180-S: |
Designer of special clone of the Z180 CPU. (Safe-state version
for space applications, currently flying on the Juno mission to Jupiter). |
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Rabbit I/O: |
Designer of multi-function I/O chip. (Counting, timing, PWM, Quadrature
decode). |
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Rabbit 4000: |
Designer of third-generation microprocessor. (CPU enhanced to 32 bits
internally, optional 16-bit external bus, integrated DMA controller, and 10BASE-T network port). |
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Y8002: |
Designer of synthesizable clone of the Zilog Z8002 16-bit
microprocessor. |
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Rabbit 3000: |
Designer of second-generation microprocessor (Enhanced CPU plus
expanded complement of peripherals). |
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Z80-SIO: |
Designer of synthesizable version of the Z80-SIO. |
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Rabbit 2000: |
Designer of enhanced Z180 microprocessor (CPU plus full complement of
peripherals). |
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DMA: |
Architect/designer of 32-bit DMA controller for an FPGA vendor. |
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UART: |
Designer of 8250/16450 compatible UART for an FPGA vendor. |
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Y180: |
Designer of synthesizable clone of the Z180 microprocessor (CPU
only). |
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Zilog, Inc. 1978-1995. Held positions as a Design
Engineer, Senior Engineer, Staff Engineer, Senior Staff Engineer, Project Leader, Fellow,
Director of Architecture, and Senior Technology Fellow. Supervised from one to twenty-five
engineers and layout designers at different times, working on these projects: |
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Z89300: |
Consulting engineer for this family of television controllers. These
devices contain an embedded DSP and control all aspects of TV operation. |
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Z87001: |
Consulting engineer for this single-chip spread-spectrum telephone chip.
This device contains an embedded DSP to control all aspects of the telephone operation. |
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Z380: |
Architect and a designer of this microprocessor, a 16/32 bit upgrade of
the original Z80 microprocessor. |
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Z86C93: |
Designer of the search engine for this Hard Disk controller. The search
engine manages the cache on the hard disk controller. |
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Z16C32: |
Architect and a designer of the IUSC. This 10Mbit/sec serial controller
contains an intelligent DMA to manage the data transfer. |
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Z16C35: |
Architect and designer of the ISCC. This chip joins the Z85C30 SCC with a
DMA controller. |
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Z85C80: |
Designer of this combination of the Z85C30 SCC and a SCSI controller. |
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Z16C30: |
Architect and a designer of the USC. An advanced 10MBit/sec multi-
protocol serial controller. |
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Z85C30: |
Contributed to the CMOS conversion of this device by an outside design
house. |
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Z280: |
Contributed to the design of this microprocessor. I designed the UART,
memory control, cache control, and refresh control, and debugged the execution unit. |
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Z8003: |
Contributed to the design of this microprocessor. I was primarily
responsible for the simulation of the device, using an in-house simulator. |
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Z8015: |
Verified the logic design of this Memory Management Unit. This predated
simulators and was done entirely by hand. |
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Z8530: |
Designer of this Serial Communications Controller. I designed the device,
did most of the layout, wrote the tech manual and the test programs. |
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Skills: |
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Experienced Verilog HDL user. |
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Experienced Synopsys synthesis tool user. |
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Altera, Lattice, MicroSemi and Xilinx FPGA Design tools. |
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C, BASIC and assembly language for Z80/Z180, Z8000 and Rabbit microprocessors. |
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Familiar with most serial protocols, at least at the bit
level. |
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Amateur Extra amateur radio license (KR6DC). |
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GMDSS Maintainer commercial radio license (DM00000647). |
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Professional Associations: |
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Life Senior Member IEEE; Member Phi Beta Kappa, Tau Beta Pi and Eta Kappa
Nu. |
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Patents and Publications: |
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17 U.S. patents granted. |
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Inside An Open-Source Processor: An Introduction to RISC-V, ISBN 978-3-89576-443-1, 2021 |
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Microprocessor Design Using Verilog HDL, ISBN 978-0-9630133-5-4, 2012 |
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"Creating the 41CL Calculator" chapter in RCL40, ISBN 978-0-9510733-4-6, 2022 |
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Inside An Open-Source Processor, Elektor Magazine, January/February 2022 |
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Comparing FPGA Technologies, Circuit Cellar, December 2015 |
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Secure Hash Standard, Circuit Cellar, September 2015 |
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Notable Contributors: Monte Dalrymple, Circuit Cellar 25th Anniversary Issue, 2013 |
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Calculator Brain Transplant, Circuit Cellar, October 2010 |
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Advanced Encryption Standard, Circuit Cellar, February 2010 |
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The Evolution of Rabbits, Circuit Cellar, December 2009 |
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Robotics Made Easy, Circuit Cellar, March 2008 |
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Designing for Hostile Environments, Circuit Cellar, January 2008 |
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Cyclic Redundancy Check, Circuit Cellar, August 2006 |
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Third Generation Rabbit, Circuit Cellar, January 2006 |
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Rolling Your Own Microprocessor: Part 2, Circuit Cellar, October 1999 |
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Rolling Your Own Microprocessor: Part 1, Circuit Cellar, September 1999 |
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Updating a Classic: the Z80380 Microprocessor, Circuit Cellar, February 1996 |
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Towards a Serial Communications Subsystem: the Z-SCC, COMPCON
1980 |