Systemyde (pronounced system-wide) International Corporation develops Intellectual Property (IP), in the form of synthesizable Verilog HDL models.

I do contract design work. If you have a project that can benefit from an experienced IC or FPGA designer please contact me, as I am currently available for new projects.

I have a broad range of design experience, but am particularly familiar with 8-bit and 16-bit microprocessors and peripheral controllers.

My Verilog HDL designs are suitable for FPGA, ASIC or full custom implementations.

I designed all five generations of Rabbit microprocessors and my contract with Rabbit Semiconductor gives Systemyde full core rights to these designs.

The Rabbit 2000, Rabbit 3000, Rabbit 4000, Rabbit 5000 and the Rabbit 6000 are the core technology for what is currently a $19M/quarter business. The first three generations are completely foundry- and technology-independent, while portions of last two generations are currently tied to a specific technology/fab because of analog IP.

With the Rabbit designs, I wrote the specification, did the majority of the architectural work, wrote all (or almost all, for the 5000 and 6000) of the Verilog HDL, wrote the testbenches and simulation/test vectors, defined and inserted test controllers, prepared the designs for scan insertion, and contributed to timing closure.