41CL Calculator

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05/31/2024 Status:
Updated images: CEPH, FLDB, FRML, LEPH, SM44, ZC2B

05/08/2024 Status:
New images: BFL5

Built 50 serial connectors and 50 serial cables. Now I just need to program the FPGA, program the CPLD, solder the piezo buzzer, program the Time Clone, solder the Time Clone to the CL board, update the Flash, and do the final test for all 50 boards. Then I can start shipping.

03/25/2024 Status:
Updated images: CEPH, FLDB, IMDB, LEPH, WARP
New images: HPXQ, RCLT, ZC2B

03/05/2024 Status:
Updated images: CEPH, DASM, FLDB, LBLS, LEPH

Last batch is at the assembly house. I guess it's time to start making the serial connectors and serial cables. I can't believe the first batch of boards went out for assembly back in 2011!

01/09/2024 Status:
Updated images: CEPH, FLDB, LEPH, XPMM

11/26/2023 Status:
Updated images: CEPH, FLDB, LEPH

Still no progress on the next batch. Still sorry. Health issues.

09/28/2023 Status:
Updated images: CEPH, FLDB, LEPH

Still no progress on the next batch. Still sorry.

07/25/2023 Status:
Updated images: CEPH, FLDB, LEPH, XPMM

No progress on the next batch. Sorry.

07/06/2023 Status:
Updated images: 16CS, CEPH, FLDB, LEPH

All components for the next batch are in hand. Will try to remember how to program the Flash memory next week. Will also ask for a quote on assembly.

06/02/2023 Status:
Updated images: 16CS, 4AOS, CEPH, FLDB, LEPH, XMPP

05/19/2023 Status:
Finally found a source for the Flash memory device.
I have orders in hand for all 50 boards from the batch I am working on. You are welcome to send in an order form, but unless someone backs out, (which, historically, happens about 30% of the time) I may not be able to fulfill the order.

04/28/2023 Status:
Updated images: CEPH, FLDB, IMDB, LEPH, WXTI, XMTW
New images: CIPW, HAMZ, ODES, PROJ

Building Flash image for next batch. Manual process, slow-going. Hope I remember how to program the FPGAs after the batch is assembled. Still looking for source for Flash memory device. Batch will be 50 boards, with 49 already spoken for.

04/04/2023 Status:
New images: XSEJ, XTVZ

41CL components ordered. June delivery.

02/23/2023 Status:

Pondering ordering components for another 41CL batch.
MAXX -3A Manual released.

02/06/2023 Status:
New images: 4AOS, XRGQ

MAXX module is out for beta test. Watch for the -2C manual coming soon.

01/09/2023 Status:
Updated images: CEPH, FLDB, IMDB, LEPH, WRAN, XMTW, XPIY, XSM4, XZ41
New image: WXTI

12/14/2022 Status:
New images: Lots of them, for use with new banked LIBRARY-4

10/27/2022 Status:
Updated images: CEPH, FLDB, LEPH, TVMY

09/23/2022 Status:
Updated images: CEPH, FLDB, FRML, IMDB, LEPH, SLVF
New images: MWK9, TCHA
Relocated image: AV1Q

07/22/2022 Status:
New image: IMDC

06/29/2022 Status:
New images: XMMA, XMPP, XMXF

06/05/2022 Status:
Updated images: CEPH, FLDB, IMDB, LEPH, YPRT
New images: MPOW, XMTW

There are places in China that say they have the Xilinx part in stock. Sorry, I'll wait for stock from an authorized distributer.

04/25/2022 Status:
Relocated images: BBSC, CMT1

HDD failure last month, still trying to recover. All of my 41CL stuff was on that disk and my last backup was some time ago. What a pain.

ETA for the Xilinx part used in the 41CL is January 2024! Most of the other parts are later this year at the earliest. Obviously there won't be any more 41CL boards any time soon, if ever. But I do have a waiting list, so feel free to send in an order, just in case.

03/04/2022 Status:
New images: ASTL, GONH, SOLS

01/23/2022 Status:
Updated images: CEPH, FLDB, IMDB, LEPH, OSX3
New images: CMPZ, RNDZ
Relocated images: MTST, TRIH
All 41CL boards have been sold. You are welcome to submit an order, but I don't know when (or if) there will be another batch.

12/21/2021 Status:
Updated images: CEPH, FLDB, LEPH, METX, NYSB

11/15/2021 Status:
Updated images: FLDB, IMDB, METX, NYSB
New images: DIVE, OSBK, UTIL
Renamed Image: 3SWP -> SWP3
New mnemonics: YFNC (points at page 0x80C in RAM), YFNY (points at page 0x1F8 in Flash)
There are eight 41CL boards remaining.

10/31/2021 Status:
Updated images: CEPH, FLDB, LEPH

10/05/2021 Status:
Updated images: CEPH, FLDB, LEPH, XPMM

09/06/2021 Status:
Updated images: CEPH, FLDB, IMDB, LEPH
New image: GAMF

07/31/2021 Status:
Updated images: 4ALP, CEPH, FLDB, IMDB, LEPH
New image: UPBB
If you're interested in what I've been doing for the past year: my book

07/07/2021 Status:
Updated images: 4LIB, CEPH, CRTO, FLDB, IMDB, LEPH, SM44, WARP, XPMM
New image: TTOU

06/02/2021 Status:
Updated images: CEPH, CRTO, FLDB, LEPH, RCSN

05/17/2021 Status:
Updated images: CEPH, FLDB, IMDB, LEPH, OSX3, WARP
New image: JMBA

04/04/2021 Status:
Updated images: CEPH, FLDB, HEP2, IMDB, LEPH, OSX3, PWRX
New image: HEP3
Relocated image: HDIS

The serial cable is no longer available, so I'm going to need to make them myself. Parts cost a little more than pre-made.

03/03/2021 Status:
Updated images: CEPH, FLDB, LEPH

02/09/2021 Status:
Updated images: 4LIB, 4MTI, ADVG, CEPH, FLDB, LEPH, ZMAT

A batch of 41CL boards and a batch of FHM boards are both out for assembly. Expected back at the end of February, but then they need to be programmed.

01/05/2021 Status:

The OS sector update is NOT critical. The OS41 changes are the bug fixes from Hakan Thorngren. The TMOD changes are to make execution slightly faster in Turbo mode. The YFNZ fix is for a bug in the YGETUB function.

12/15/2020 Status:
I won't be able to start the next batch until after Christmas, so don't expect boards to be available until the end of January at the earliest. Just received notification that the Flash device is EOL.

12/08/2020 Status:
Updated images: 4FTH, 4OS4, BSTZ, CEPH, FLDB, FRTH, IMDB, LEPH

11/02/2020 Status:
Updated images: 4MTI, CEPH, FLDB, INDO, LEPH, Z4DL, ZMAT

All of the current batch have been sold. Planning on starting another batch in the next few weeks.

10/03/2020 Status:
Relocated images: ZONE, AOSX

09/04/2020 Status:
Updated images: CEPH, EPIV, FLDB, IMDB, LEPH, Z4DL
Relocated images: EPIV, RMPG

08/08/2020 Status:
If you are using UPDAT-4B or UPDAT-4C to update V3/V4 boards DO NOT USE the "*" option for the FLUPD function. Instead, specify "008>1FF" for the range.
Updated images: 4MTI, CEPH, EPIV, FLDB, LEPH, RCSN, YUPS

07/24/2020 Status:
The problem with UPDAT-4x only affects V3/V4 boards. The bug causes the FLUPD function with the "*" option to skip pages 0x000 - 0x07F when updating out-of-date pages. Now to track down why...

UPDATE: Well, it finally happened. I ran into one of those boundary cases for the C=G instruction. (Number 4 in the NEWT manual for those interested.) So UPDAT-4D will be in the next release.

07/11/2020 Status:

07/06/2020 Status:
Updated images: CEPH, FLDB, IMDB, LEPH, YUPS

Rearranged a number of images in Flash to make more useful ones available in V3 and V4 boards.

Modified 41CL Update Functions to skip writing words of 0xFFFF to save some time.

05/31/2020 Status:
New image: BSTZ, HELP
Renamed HCMP to COMP to make room for HELP

Rearranged a number of images in Flash to make more useful ones available in V3 and V4 boards.

Modified 41CL Update Functions to skip sectors at top of Flash so that user backups don't get clobbered by accident.

05/02/2020 Status:
New image: EPIV
Updated images: 4LIB, CEPH, FLDB, FRML, IMDB, LEPH, WARP

04/01/2020 Status:
New image: HELI
Updated images: 4LIB, CEPH, FLDB, IMDB, LEPH, WARP
Batch is in the mail from the assembly house.

03/01/2020 Status:
New image: ADVP

02/01/2020 Status:
New images: DURU
Updated images: 4MTI, ADVG, CEPH, CHES, DURR, FLDB, IMDB, SM44, ZMAT

All of the current batch are gone. I'll try to have another batch ready in March.

01/01/2020 Status:
New images: BNBD, ZMAT
Updated images: 4MTI, ADVG, CEPH, FLDB, IMDB, HT41, HTP5, SM44, Z4DL

12/04/2019 Status:
Successfully made some 41CL front labels. If you didn't get one with your board, they'll be in the mail tomorrow.

I have three boards left from this batch. Haven't decided if I should try to do another batch.

12/03/2019 Status:
Updated images: 4MTI, FLDB

12/02/2019 Status:
Updated images: 4MTI, ADVG, FLDB, SM44

11/04/2019 Status:
Updated images: FLDB, IMDB, SM44, UNIT, WARP
New image: BBDY

I also moved a few obscure images out of prime V3/V4 real estate into addresses only present in V5 machines.

10/27/2019 Status:
Updated images: CEPH, FLDB, IMDB, LEPH, OSX3
New images: HT41, HTP5, YSV1, YSV2, YSV3

The YSV1/2/3 images are the HP service modules, modified so that the "0" key disables the MMU, which allows you to then program the MMU to remove the service module. Otherwise you have to remove the batteries to get the MMU disabled, which is kind of a pain.

09/30/2019 Status:
Updated images: 16CS, ADVG, CEPH, FLDB, LADY, LEPH, OSX3, PWRX, SM44, WARP, XPMM, Z4DL

Built the two varieties of the Service Module out of the FHM. Woohoo!

09/04/2019 Status:
Updated images: FLDB, OSX3, SM44

09/01/2019 Status:
Updated images: FLDB, SM44, WARP, XPMM

08/28/2019 Status:
New images: ENG2, GMAN, LNDR, MIND, NASA, SVY2
Updated images: 4LIB, 4MTI, CEPH, FLDB, FRML, IMDB, LEPH, PWRX, SM44, YLIB

07/31/2019 Status:
Updated images: 16CS, 4LIB, FLDB, HEP2, OSX3, XPMM

I think I know the problem with the Time Clone, but I still need to verify the fix on the breadboard.

07/29/2019 Status:
I have received a critical update to 4LIB, HEP2, OSX3 and XPMM. Expect a special Flash update shortly.

I have received a report of a bug in the Time Clone. Normal alarms work fine, but the Timer Alarm (which I wasn't even aware of, and thus didn't test) does not. This is a hardware issue that I am still investigating.

07/23/2019 Status:

06/27/2019 Status:
Updated images: FLDB, WARP

06/26/2019 Status:
New image: WLP5

06/10/2019 Status:
All boards in the batch updated. Shipped all existing orders that have been paid for. But I have run out of front labels. Time to try to make my own. Then perhaps I can get back to the GNSS module.

05/29/2019 Status:
Piezo buzzers attached, CPLDs programmed and FPGAs programmed on the entire batch. Flash updated (a 61-minute-per-board operation) on half of the batch. Attaching Time clones to some of the boards now.

05/23/2019 Status:
Updated images: 4ALP, CHES, FLDB, IMDB

05/16/2019 Status:
Latest batch is back from the assembly house.

05/11/2019 Status:
Still no shipment notification from the assembly house.

05/01/2019 Status:
New image: 2CHM
Updated images: FLDB, IMDB, 4ALP

04/30/2019 Status:
New images: FUNP, LPLX, TOOL, WLAA
All these changes will mean about 45 minutes per board to update the Flash, so it's going to take a while to catch up on pending orders. Please be patient.

04/13/2019 Status:
Batch of 41CL boards are out for assembly. I expect them back around May 10th. Then it takes a few days to program the FPGA and CPLD, attach the buzzer, and then test the boards and update the Flash.

03/27/2019 Status:
New images: CEPH
Updated images: FLDB, FRML, IMDB, 4LIB, SLVF

02/21/2019 Status:
New images: FRMX, GLNG, SLVF
Updated images: FLDB, FRML, IMDB, YLIB
Was able to procure parts, and am preparing to send another batch of 41CL boards out for assembly.

1/9/2019 Status:
The problem with the Time clone is not related to a 41CL update. What happens is that sometimes when new batteries are inserted the FPGA, for some reason, draws about 75mA of current. This is even though the chip functions correctly. The only indication that something is wrong is that the CL doesn't turn on properly with the first press of "ON". I believe that the root cause has something to do with the ramp rate of the power supplied to the FPGA. I am evaluating a possible fix right now.

1/1/2019 Status:
A user has reported a problem when updating the CL on a board with the Time Clone installed. I tried an update on a similar board and have seen the same thing. The machine eats the batteries during the update. I am suspending shipments of the Time Clone until I figure out what is going on. This may take a while, because debugging this is going to be extremely challenging.

12/28/2018 Status:
Updated images: YFNX, YLIB, YUPS, YFNF
I think this fixes all of the problems (YFNX & YLIB), and adds new features (YUPS & YFNF). Refer to the updated documentation for the details.
I just noticed that the distributor (Digi-Key) will no longer carry the FPGA that I use in the FHM. Great.
I think that all of the latest batch are spoken for. You can still send in an order but I don't know when (or if) there will be another one.

12/15/2018 Status:
In addition to breaking TURBO and BAUD, I also managed to break EXCFG, RCLCFG and STOCFG. That's what happens when you've forgotten that no status can be passed past a partial-key sequence. Unbelievable. So it's back to the drawing board.

12/11/2018 Status:
And of course my fix for the TURBO function in YFNX-4A broke the BAUD function. Expect an update as soon as I figure out how to fix it for good.

12/03/2018 Status:
New images: ELIB, MWK5
Updated images: FRML, OS41, OSX3, PWRX, TMOD, WARP, YFNX (plus IMDB, FLDB)

11/30/2018 Status:
A user (thank you, Kari Pasanen from Finland) has identified two problems with the Time Clone. A write-up describing these two problems and possible work-arounds can be found here (.pdf).

11/22/2018 Status:
The TURBO function in YFNX-4A doesn't work. Broke it while making room for the extra code to support more configurations. PTURBO works fine though, so use it for now.

A user has reported a problem when using the Time clone. It seems that the CLOCK function doesn't remember the CLK24 or CLKTD states after the 41CL has been turned off. But I think that the real problem is something to do with the Turbo mode. Investigating

11/09/2018 Status:
I pushed out an update yesterday because there was a critical bug in the WARP image. But that update had errors in it, so I deleted it and replaced it with a corrected version today. Sorry about that.

11/08/2018 Status:
New images: ABRD, DURR, E3AF, IRSU, MINV, MLMU, 120M
Updated images: WARP (plus IMDB, FLDB)
Still thinking about how to supply the default configurations.

11/02/2018 Status:
Updated images: BASI, GAMX, OSX3, NONL, WARP, YFNX, YLIB (plus IMDB, FLDB)
Relocated images: E-6A, TGT3
The top sector on V4 boards is now empty, so users can customize it as they like.
The changes to YFNX and YLIB increase the number of alternate configurations from 3 to 15. I'll be updating the manuals soon, but it operates the same as before. I plan to add a set of default configurations that you can use as a starting point if you want.

10/24/2018 Status:
Link to 'Angel Martin's Alschwill 2018 presentation (.pdf).

10/11/2018 Status:
Link to my HHC 2018 presentation (.pdf).
Link to a video of my HHC 2018 presentation.

10/01/2018 Status:
I added an "Update Archive" page with all of the previous rom_files_xxxxxx.zip so that you can use clupdate --diff to see the change history. This will help when doing incremental updates.

I have been doing updates whenever I received a new or modified .rom file. But it takes a couple of hours of manual processing to do a release, so I will probably start accumulating changes and just do a once-a-month update.

09/28/2018 Status:
Updated images: ADVG and SM44 (and FLDB)

09/25/2018 Status:
New image: FSTK
Updated image: RRAP (and IMDB, FLDB)

09/24/2018 Status:
Updated FLDB_V2.ROM and mem_ref_v2.txt to fix error. Sorry about that.

09/23/2018 Status:
Updated IMDB and FLDB to correct an error (thank you, 'Angel.)

09/22/2018 Status:
New images: LTLN, PAPZ, RRAP

I expect to get some more front labels in a week. I'll send out one to everyone who didn't get one with their 41CL recently.

09/17/2018 Status:
Updated images: FRML, 4LIB, HEP2, OSX3, 4MTI, PWRX, XPMM, SM44, WARP, 16CS, Z4DL
New images: SDMO, BEPT
Deleted Image: MTRA
Relocated image: 2SWP

08/28/2018 Status:
Cleared the backlog of regular CL boards. Now working on mounting Time Clone modules onto the boards for those wanting that option. Takes some time, so please be patient.

I have run out of the 41CL front labels. I may try to purchase the equipment to make my own. If I go that route I will send you one when (or if) I can.

08/23/2018 Status:
Shipping the latest batch of CL boards. As usual, 40% of the people who sent in an order form don't respond when I contact them to verify the order. And every non-response is in the US. Go figure.

08/11/2018 Status:
Batch of CL boards will arrive 8/13. Mounting the Time Clone board on a module connector is difficult. Tried twice, somehow irreversibly damaged both boards. So no beta testing (or eventual product release) unless I can figure out what happened. Frustrating.

08/06/2018 Status:
The assembly house informs me that the batch will SHIP on the 10th. So I don't expect to see it until about the 15th or 16th, because it is coming by ground, from halfway across the country. A couple of Time Clones will go out for beta testing shortly. Here is a photo of the Time Clone affixed to a CL board.

07/27/2018 Status:
The Time Clone is in my calculator, keeping time. Now I need to start verifying all the features. Hopefully I can finish before the CL boards come back on the 10th and start monopolizing my time with soldering, programming, testing, invoicing and shipping.

07/12/2018 Status:
Batch out for assembly. 20 day turn time.

07/06/2018 Status:
Updated images: CURV, PPC9, VONK, WARP
New images: LUIZ, MAZZ

07/01/2018 Status:
Updated images: SM44, Z4DL

06/30/2018 Status:
Fixed a missing entry in the IMDB: QMTH

06/26/2018 Status:
New image: BREF

06/24/2018 Status:
New image: QMTH
Updated images: ADVG, RCSN, 4MTI

06/21/2018 Status:
Updated images: IGSW, YUIL, 4MTI

06/12/2018 Status:
One updated image: 4MTI

06/10/2018 Status:
Fixed an error in FLDB and mem_ref (thank you, Sylvain.) Added image of the printer functions portion of the HP-IL Module for completeness.

06/02/2018 Status:
Ordered parts for another batch. But one single-sourced part is out of stock until July. Another is out of stock until October!

05/17/2018 Status:
Thinking about doing another batch of CL boards, if I can find all the parts (or substitutes).

05/14/2018 Status:
A couple of updates and several new images.

04/24/2018 Status:
Several updates and one new image.

04/02/2018 Status:
One update and one new image.

03/22/2018 Status:
A few updates and one new image.

03/11/2018 Status:
A couple of updates and new images.

02/23/2018 Status:
Fixed a couple of bugs in the IMDB.

02/16/2018 Status:
A number of updates and new images.

01/23/2018 Status:
Three more updates. The latest updates are always marked in the mem_ref documents and the images are always available in the rom_files zip file. I'm not going to continue maintaining the individual image files, and the ones that are here will eventually go away.

01/22/2018 Status:
Large set of updates and new images.

01/03/2018 Status:
YFNX-3A is out for beta testing. Rearranged FAT to make it more "compatible" with YFNZ.
All of the V5 boards have found homes. Another batch depends on sourcing EOL components.

12/03/2017 Status:
Updated version of the clupdate software added.

12/02/2017 Status:
Updated image: WARP.

12/01/2017 Status:
Updated images: METX, PWRX, WARP.
New image: YUIL.
Also, YLIB has been updated to -3C, to fix a bug related to querying the MMU with PLUG function options.

11/23/2017 Status:
New images: MRTR, P18E.

11/21/2017 Status:
Someone finally noticed, and complained, that the silkscreen on V5 boards still says "V4". The PCB Fab house screwed up and didn't use the updated silkscreen layer. Fixing it wasn't worth ordering another batch of boards. You can tell a V5 visually because the Flash device is a M29W640. The FLASH? command will also confirm that it is a V5 board because the Flash ID code will return the code for that device. I was just waiting for someone to notice.

11/19/2017 Status:
Added the source files and merge program to IMDB.ZIP in case anyone wants to do a custom memory map.

11/17/2017 Status:
Fixed a filename typo in the V5 memory reference (thank you, Sylvain.)

11/07/2017 Status:
There are some obsolete pages in the Flash memory of V5 boards that were shipped before yesterday. There is also a problem with the UPDAT-3A software. The details can be found here.

11/01/2017 Status:
V5 boards are shipping.

10/24/2017 Status:
New image: BDRV.
V5 batch back from assembly.
Timer clone PCB ready for fab.

10/01/2017 Status:
Obsolete image: Z41Z.
New image: BIDQ.
Released Clone Functions.

09/23/2017 Status:
Updated image: YUPS.
V5 batch out for assembly. Expected back 10/20/17.

09/14/2017 Status:
Updated image: METX.
Hope to be able to send V5 batch out for assembly next week.

09/11/2017 Status:
New images: BELP, RDII.
Updated image: YFNF.

08/15/2017 Status:
New image: 5PAR.

08/11/2017 Status:
Fixed yet another bug in the update functions.

08/07/2017 Status:
Fixed a bug in the update functions.

Still debugging the Time Module clone. Time, Date, Stopwatch, Alarms and Accuracy Factor all working. Corner cases for clock switching verified. Still need to look at clock domain crossing again. Also need to verify that the ROM is working. Slow-going because of limited visibility for internal signals.

08/04/2017 Status:
Updated images: FRML, SM44, WARP.
Added package of Mark Fleming's "GPS for the 41CL" project. Check it out!

V5 bare PCBs received. Thinking about when to do another assembly.

Still debugging the Time Module clone. Time and date functions are working. Still need to look at Stopwatch, Alarms, accuracy factor, corner cases for clock switching and clock domain crossing. Slow-going because of limited visibility for internal signals.

07/08/2017 Status:
Deleted obsolete image: CCDP.
Updated image: FRML.
Ordered V5 PCBs.

07/04/2017 Status:
New image: BPDE.

06/30/2017 Status:
The stand-alone FPGA programming software does accept the existing bit file, so I am still able to program the FPGA on the board. But if I ever need to change the design I'll need to recreate everything in the new version of the design software.

06/29/2017 Status:
Went to reprogram the FPGA on a beta V2 board that someone sent back for updating. Except the license file for the FPGA software has expired and the manufacturer will no longer issue license files for that version of the software. Add to this the fact that the newer version of the software will not import the old project files. I have to start from scratch with the HDL files and then recreate all of the constraint files (pinout, clock buffers, etc.) Unbelievable. And if I don't do this I can't do another batch, either.

06/28/2017 Status:
Fixed a stupid mistake in the 41CL Update Functions.

06/26/2017 Status:
Updated a bunch of stuff to work with the larger Flash memory in a possible V5 version.

06/09/2017 Status:
Deleted obsolete images: TOOL, YFNS.
New images: FRML, YUPS.
Replaced YFNS with YUPS, which is the auto-update software. Found out that the Flash memory devices used in the 41CL are Last-Time-Buy status. Need to decide how many more 41CL boards there might be.

05/27/2017 Status:
Deleted obsolete image: ALPH.
New image: WARP. This image updates and replaces the TTRC image.
Updated image: 4LIB.
Had to do a small rearrangement to accomodate the above changes. Also, there is only one more board available. Once it is gone you can still submit an order, but I don't have a date for another batch.

05/09/2017 Status:
Updated image: CHES.
New image: WPNE. This image is not loaded by default, because of space constraints. Thank you to Dan McDonald for loaning me the physical "WPN EFFECTS" module.

05/04/2017 Status:
Updated image: TTRC.

05/02/2017 Status:
New images: 5MAD, 5LON.
Obsolete image: RAMP.

04/23/2017 Status:
Updated image: METX.

04/18/2017 Status:
New image: METX.
Obsolete images: BLND and MTRX.

04/12/2017 Status:
Found and fixed a typo in the image database.
New image: IMS4. This image is not loaded by default, because of space constraints.

03/26/2017 Status:
Updated images: SERI, FRID, TGT2, TGT3.

03/24/2017 Status:
Updated image: Z4DL, SERI.
New images: FRID, RCSN, TGT2, TGT3.

02/26/2017 Status:
Updated image: Z4DL.

02/23/2017 Status:
Repaired a few MORE things in the Flash Databases and the .zip with the .rom files.

02/22/2017 Status:
Repaired a few things in the Flash Databases and the .zip with the .rom files.

02/19/2017 Status:
Updated image: FLDB_V2 because of three typos (thank you, Sylvain). Also, slightly modified the format of mem_ref.txt and mem_ref_v2.txt to make it easier to parse.

02/15/2017 Status:
Updated image: Z4DL.

02/13/2017 Status:
Updated image: Z4DL.

02/11/2017 Status:
Updated images: 3SWP, ISOL, SIHP.

01/29/2017 Status:
Fixed a typo in the FLDB.

01/24/2017 Status:
Updated images: ETS3, UNIT

01/20/2017 Status:
Updated images: ETS3, ETS4, CURV, ISOL

12/27/2016 Status:
Updated images: ETS3, ETS4, ETS9, FFEE, FUNS

12/14/2016 Status:
Updated images: ETS4, ETS5, ETS9, H67G

11/28/2016 Status:
Updated images: ETS4, ETS5, ETS9, SM44
New image: H67G

11/14/2016 Status:
Updated images: ETS5, STEQ

11/10/2016 Status:
Updated images: TEST, ETS4
New images: PPC9

11/07/2016 Status:
Updated images: TEST, ETS4
New images: E-6A, KRMK

10/26/2016 Status:
Updated images: CIVI, MENG, PHYH
Deleted obsolete images: 4AOS, 4PLY, 4MTR

10/24/2016 Status:
Updated image: HEP2

10/21/2016 Status:
Since space in the Flash is getting tight, I'm leaning towards removing YFNS and YFNP. Since YFNS merely changes the XROM number of YFNZ, you can just copy YFNZ to RAM and change the XROM to whatever you like anyway. YFNP replaces some of the FAT entries in YFNZ with IMDB stuff and the YCRC function. All of that stuff is available in YFNX. I might also modify YFNZ to add the YCRC function and a function to check the Flash size, in place of the YBPNT and YBUILD functions, which I don't think anyone has ever used (and they're in YFNX anyway.) Anyone reading this feel free to send me feedback either way.

10/09/2016 Status:
Updated image: XPMM

10/06/2016 Status:
Updated images: 4LIB, TTRC, XPMM
The FLDB has also been updated, because of these updates. I'll get to FLDB_V2 at some point.

10/03/2016 Status:
Updated FLDB so that blank and empty pages have the correct CRC value. Created one .zip file with all the images to simplify updating a 41CL.

09/17/2016 Status:
Updated image: TTRC

09/12/2016 Status:
Updated image: TTRC

09/11/2016 Status:
Updated image: TTRC

09/06/2016 Status:
Updated images: 4LIB, ROMX, XPMM
New image: 4WIN
The FLDB has not been updated yet, because I know a change to TTRC is coming, and I'll just have to update it again.

08/31/2016 Status:
Fixed dyslexic file name: GRF1

08/27/2016 Status:
Updated images: XPMM, GRF1

08/25/2016 Status:
Updated image: YRGA

08/24/2016 Status:
Deleted obsolete image: CLUT
New image: YRGA
Updated image: XPMM

08/20/2016 Status:
Notified of errors in the flash database (thank you, Sylvain): FLDB

08/19/2016 Status:
Updated image: GJMR

08/17/2016 Status:
Updated again: PWRX

08/16/2016 Status:
Updated image: PWRX

08/15/2016 Status:
Three updated images: OSX3, ROMX, XPMM

08/05/2016 Status:
Two new images: CAB4, GEOD
Three updated images: NONL, XPMM, YFNF
Boards are back from assembly, with piezo attached, CPLD and FPGA programmed. Just need to update the Flash (45 minutes per board, ugh.)

07/29/2016 Status:
Five new images: ROMX, GRF1, GRF3, GASL, GASU

07/11/2016 Status:
Modified the "Updating the 41CL Flash" document.

07/08/2016 Status:
One new image: HNDY

07/05/2016 Status:
One updated image: XPMM
Parts and bare boards shipped to assembly house today.

06/30/2016 Status:
One new image: ADVG
Two updated images (SERI and 4RAM). Preparing to order another batch of boards.

06/20/2016 Status:
One new image: 141B

06/10/2016 Status:
One new image (GAMX) and one revised image (FUNS).

06/08/2016 Status:
Two new images (DBUG and RCRD). RCRD is the Card reader ROM, which I had not previously included because it is hardware-specific. But Gene Wright pointed out that there are some routines in the image which might be useful without the card reader actually being present.

06/06/2016 Status:
Several new images (AGAM, GRMK, RGME, SR1B). Several modified images (ADV1, ADV2, 2SWP, GSB2). A couple of images went from 4k to 8k, so they had to be moved (GSWP, MAHJ, BASI). One image obsoleted (GTWN). Refer to the Memory Reference for details.

05/17/2016 Status:
New image: Outer Planets (OPLN). The holes in the Memory Reference are where I finally deleted the obsolete images to make room for new stuff. References to those images were removed from the IMDB a while ago, so nobody should still be using them.

05/13/2016 Status:
A few revised images, and several new images.

04/24/2016 Status:
New image: Games Solution Book 1/2 (GSB2). Removed obsolete image references from IMDB.

04/17/2016 Status:
New image: HEPAX Periodic Table (HTAB). Also, discovered that I managed to lose the image for the WPN Effect ROM. Incredible.

04/15/2016 Status:
New version of 41Z Deluxe.

04/12/2016 Status:
New version of 41Z Deluxe. Added link for Michael Fehlhammer's awesome overlays.

04/01/2016 Status:
All of the current batch are spoken for. I still have one V3 board and two V2 boards available. You can still submit an order for a V4 board, but I don't have a schedule for when more boards will be available.

03/18/2016 Status:
New version of 41Z Deluxe.

03/06/2016 Status:
New mnemonic (Z4DL) and version of 41Z Deluxe.

03/04/2016 Status:
New versions of several images, and a couple of new images.

01/25/2016 Status:
Updated versions of SM44 image and documentation.

01/20/2016 Status:
Remember the CL that wouldn't work after the PC it was connected to went to sleep? The one where the CL board worked in a different calculator body? It's been sitting on my desk, assembled, for a week. On a whim I inserted the batteries and turned it on and presto - "MEMORY LOST." Incredible. It had to have been some wierd state being retained in the display driver chips, or some kind of memory mechanism with the batteries.

01/18/2016 Status:
Added updated Sandmath 4x4, plus two new images.

01/11/2016 Status:
Updates for revised Library-4. I still haven't figured out what happened when the PC went to sleep with a 41CL connected. The board works fine in a different calculator body. Grr... makes no sense.

01/04/2016 Status:
Two modified images. Fixed a typo in IMDB (thanks, 'Angel.) Making serial connectors today.

01/03/2016 Status:
Revised the Updating the 41CL Flash document. It turns out that you need to be careful with the serial port. My PC went to sleep while I had the serial port connected, and now the 41CL doesn't work! The only thing I can think of is that a voltage transient somehow made it to the CPLD.

01/02/2016 Status:
Revised the Updating the 41CL Flash document. Updated the 41CL Memory Functions to -1D to fix a problem displaying the address and data with YPOKE+ and YPEEK+ functions. The functions worked properly, but the display of the result was messed up for one character.

12/30/2015 Status:
Revised the Updating the 41CL Flash document. There is a problem with the method used to determine if you have one of the early V3 boards. It looks like the YPOKE with a Flash destination isn't working for some reason. I'll post an update when I figure out the problem.

12/29/2015 Status:
Updated the 41CL Dynamic Library to -3A to add more options for the PPLUG function when using a direct page address. If you never do this, the update is not necessary.

12/25/2015 Status:
Updated the "Other Docs" page with more documentation.

12/18/2015 Status:
More new images.

12/07/2015 Status:
Added some new images. Tweaks to various documentation. Also, check out my article comparing FPGA technologies in the December Circuit Cellar magazine.

12/01/2015 Status:
Released the Updating the 41CL Flash document. Feedback welcome.

11/16/2015 Status:
More new images added to the memory map.

10/28/2015 Status:
Added a few new images to the memory map. Working on a "Flash Updating for Dummies" paper. Noticed something I don't like about the "PLUG? ?IMG ?" function with the V2 version of the Image Database, which has a bunch of NULLed entries. Pondering whether or not it's worth fixing.

10/13/2015 Status:
Finally took the time to try serial port downloads to the 41CL. Works fine using CLWriter. Even managed to update the OS sector on a customer machine without bricking the machine!

10/10/2015 Status:
Used serial CL-to-CL transfers to update my machines. Managed to mess up twice. The first time I was using YFNX on the target machine and erased the sector containing YFNX. Dumb. Then on another machine I forgot that I had the 4LIB loaded via the MMU. Erased the sector containing 4LIB, which locked up the machine. After reset I enable the MMU, only to have the machine lock up again. Took me a couple of tries before I realized that I had to clear the 4LIB MMU entry manually before enabling the MMU. I should probably put a note about this in the manual.

10/06/2015 Status:
YLIB updated to -2H. Fixes the case where if an IMDB? group search was attempted with an illegal group identifier the machine would exit with the Turbo mode set to 50. Obscure, and not an issue for most people.

10/05/2015 Status:
Looking into an issue with YFNX. If an IMDB? search is terminated early it seems that the machine stays in the 50x Turbo mode that is automatically entered for the search. Grr...

09/18/2015 Status:
Discovered a bug in YFNF-1B. The YPEEK+ and YPOKE+ functions work properly, but don't return the correct result to the display or Alpha register: the four most-significant digits of the pointer are reported as "0000" even though the pointer is correct in memory. Fixed in YFNF-1C.

09/14/2015 Status:
I guess nobody except me is using YFNX... otherwise they would have noticed the minor bug. It's not really a big deal, but it's fixed now. It has to do with EXCFG/RCLCFG 0 reporting locked pages. If page 4 is locked it returned a "3" where it should have returned a "4".

09/10/2015 Status:
One of yesterday's images got modified, so the flash database and the memory reference got modified.

09/09/2015 Status:
A few more images added to the memory map. The 3-D printed serial port covers look good, so that's what I'll be supplying from now on. If you're interested in how the Secure Hash Algorithm works, check out my article in the September Circuit Cellar magazine.

09/02/2015 Status:
Check out the HP-16C Emulator Manual for the lastest of 'Angel Martin's contributions to the 41C universe! Now I only need one calculator (a 41CL, obviously) on my desk.

08/20/2015 Status:
Nate Martin was gracious to modify his 3-d Port cover model for me to hold the serial connector, and I have a couple of test articles on order from Shapeways. Yeah! No more spending 10 minutes each to modify a Port cover (and screwing up about 10% of the time.) But not much progress on the Time module clone - I've been working on a couple of magazine articles. I did realize that I should use a different FPGA development board, though, and got the breadboard ready for the change.

07/21/2015 Status:
Batch of boards is back, and have shipped the first few. Finally got the Timer clone to compile, (using a non-default synthesis option, thank you) and am almost ready to try it in the breadboard. Fingers crossed. Also thinking about 3-d printing some Port covers to hold the serial connector.

07/08/2015 Status:
So the design wouldn't compile using the default logic synthesis tool. Support finally comes back with "It works fine using this (alternate) tool." Might have been nice to mention that somewhere. So now the design compiles, and the placement finishes without error, but the routing fails, complaining about a net that I can't even find in the design. Another question for Support.

07/01/2015 Status:
It turns out that all of the xxCFG 0 functions have a problem. I inadvertently introduced the bug when I modified the functions to include Page 4, which requires special handling. I think that YLIB-2F corrects the issue. Thank you to Christophe Gottheimer for noticing the bug.

06/30/2015 Status:
There is a bug in YLIB (used by YFNX) around the EXCFG 0 function. Until I figure out how to fix it, you can work around the problem by always applying the Lock status to Page 4 before attempting to use this function.

06/19/2015 Status:
I have to use a different FPGA vendor for the Time module clone. I notice that the date on the datasheet is recent, so I take a look... and find the statement "Address 0 cannot be initialized" buried in it. This means that the embedded memories need special handling to be used as a ROM, which is something I need. Incredible, because this restriction isn't even mentioned in the "Memory Usage Guide." So now I'm wondering what other obscure notices are buried in the spec. Time for some very careful reading.

06/12/2015 Status:
Updated the software page to reference .zip files for easier downloading.

06/05/2015 Status:
Looked at the code for the Time Module clone. My first thought was "Why in the heck did I do it that way?" After an hour of thinking, I realized that it was an artifact of my first implementation in CPLDs, which have different constraints from FPGAs. So now the design is cleaned up and ready to breadboard in a Lattice FPGA.

05/27/2015 Status:
Okay, ordered parts for another batch. But now I need to get more front labels created.

05/18/2015 Status:
All of the current batch are gone or spoken for. You can still submit an order, but at this point I don't know when I'll do another batch.

04/29/2015 Status:
Updated the Image database with two new images.

04/07/2015 Status:
Added another column to the Memory Reference documents (thank you, Gene).

03/13/2015 Status:
Fixed some typos (thank you, Gene) and inconsistencies in the Memory Reference documents. Also discovered that I forgot to include a couple of changes in the Flash image. Grr...

03/09/2015 Status:
One more revised image.

03/03/2015 Status:
Wait for it... two more revised images. Down to my last 3 boards. Added tab-delimited text versions of the memory reference documents.

03/01/2015 Status:
One new image, plus a couple of revised images.

02/26/2015 Status:
Updated Memory Reference for V2 boards. IMDB_V2 update to follow.

02/24/2015 Status:
More new images added or updated.

02/23/2015 Status:
More new images added.

02/11/2015 Status:
41CL Memory Functions released to Beta test after I added a few more functions. Updated several manuals for revised and new images.

02/06/2015 Status:
Found it. Assembly language can be very unforgiving of typos. (I already knew that.) 41CL Memory Functions is ready for Beta testing.

01/31/2015 Status:
Still haven't figured out HOW the software bricked the calculator. Very disturbing.

01/30/2015 Status:
...and I just bricked my calculator. Debugging time.

01/29/2015 Status:
Plugging away at testing the 41CL Memory Functions. About half done.

01/19/2015 Status:
Updated several manuals to include new images. Will load 41CL Memory Functions on a machine today to see how it works on real hardware.

01/16/2015 Status:
Preliminary manual for 41CL Memory Functions is available. Code itself is in Alpha.

12/29/2014 Status:
Updated manuals for PowerCL, SandMath and SandMatrix modules (thank you, 'Angel Martin) are available on the "Documents" page. I'm now working on the 41CL Memory Functions, which will finally make the Flash Database useful. The lost package to South Africa was eventually found. Turns out a postal worker strike there meant that over 40 million packages piled up, undelivered.

11/22/2014 Status:
WARNING! Never attempt to use YFWR or YFERASE on a Flash address in the OS area, or outside of the valid Flash address range. Acceptable Flash addresses are from 0x008000-0x0FFFFF for V2 boards and 0x008000-0x1FFFFF for V3 and V4 boards. The Flash address is not fully decoded in hardware, which means that addresses outside of the normal range will wrap around into the valid range. In addition, my "fix" for the OS area check isn't quite right. The newest versions of 41CL Extra and Extreme Functions will do a range check to prevent the problem: -4E for YFNS and YFNZ, -1E for YFNP and -2B for YFNX.

10/27/2014 Status:
YFNX-2A seems to work as advertised. Time to start working on the Memory Functions image.

The Post Office finally managed to lose a shipment. Of course it was the one that had a calculator body plus two 41CL boards in it. To make matters worse, it was going to a destination (South Africa) where the Post Office will not insure packages. I think I figured out why they won't insure packges going there. What a pain.

10/07/2014 Status:
Testing YFNX-2A. The only change eliminates the need to copy the image to RAM before writing or erasing Flash. Instead, the functions automatically copy a small section of code to RAM and then execute it from RAM. Uses the existing dynamic paging code to transiently map the code in RAM to Page 4.

09/22/2014 Status:
Finally got around to updating the NEWT manual to reflect the final keyboard scanner fix. Also updated the V2 board memory map and identifier table.

09/12/2014 Status:
Total of three boards have issues. One high current (250mA), one where the Flash doesn't respond to a JTAG query, and one where the running current is about double what is normal. Strange, this is the first time I've seen any of these issues.

08/26/2014 Status:
Arghhh... Seven sectors of Flash need updating on these boards because of new images. 34 minutes per board over the JTAG port. And then one board (so far) has some kind of problem that I'll need to debug.

08/12/2014 Status:
Assembly batch is supposed to be delivered tomorrow.

07/26/2014 Status:
Latest batch out for assembly. Should be back around 8/10.

07/22/2014 Status:
Found all of the required parts. Time to start programming the Flash before sending out for assembly. On another note, after years of manually translating from .rom to Intel hex (six steps, each using a different program) I finally wrote a translation program for the PC. I also wrote a program for the PC to calculate the CRC for a .rom file. Why didn't I do this before? And on yet another note, finally got everything necessary to breadboard the Time Module clone.

07/12/2014 Status:
Rounding up parts for another assembly batch is getting interesting. Some of the parts are becoming hard to find. And the price for shipping has increased too. Bummer. On top of that, my source for Port covers doesn't have any more for me.

06/07/2014 Status:
Version -1G of the 41CL Extreme Functions and version -2E of the 41CL Library are available. These versions must be used together because of the change in how the previous Page-4 MMU contents are saved during execution.

06/02/2014 Status:
Okay, the latest version (-1F) of the 41CL Extreme Functions is completely screwed up. I have reverted to the previous (-1E) version until I get this mess cleaned up. The problem is with the handling of the Page 4 library.

04/28/2014 Status:
The latest version of the 41CL Extreme Functions has been released.

04/01/2014 Status:
Boards are available! Updated YFNX and IMDB are available on the "software" page.

03/10/2014 Status:
Batch is back from assembly. Will start testing, programming, and soldering the piezo buzzer tomorrow. Need to verify the turbo/keyboard fix before I can start shipping.

03/03/2014 Status:
Is this batch jinxed? It seems that DigiKey shipped the wrong parts for one device - but had the catalog number correct on the parts bag. So now the assembly is on hold until I can get the correct parts to the assembly house. In addition to messing up my schedule, it has inconvenienced the assemby house. They only noticed the problem because the package had the wrong number of pins. What if this happened on a passive part? That would be tough to track down. What if the wrong voltage regulator (in the right package) was shipped? That would fry the board. Arghh.....

02/19/2014 Status:
Another batch is out for assembly. I found a source for 9-pin null-modem adapters, so now you don't need a special cable for CL-CL transfers. Just use the null-modem adapter to connect two normal CL serial cables.

I have updated the order form: it's now a fillable pdf (a big thank you to Caleb Brown).

I still haven't found time to look into the keyboard issue with Turbo mode. Also, a problem has been reported with the YIMP/YEXP functions in the 41CL Extreme Functions, and I still need to look into that.

01/10/2014 Status:
It seems that the fix for the two-key rollover makes the keyboard miss keystrokes if you are running faster than 1x. This is only a problem in images that prompt for keyboard input while in Turbo mode. None of the native OS functions or 41CL Extreme Functions have a problem because in these cases the keyboard scanning is always done at 1x, even if a Turbo mode is active. I am investigating.

01/05/2014 Status:
All of the latest batch have been sold. I'll still accept orders, and once I have enough accumulated I can start another batch.

12/18/2013 Status:
Updated the "pc41.txt" Ruby script (thank you, Geir Isene) for serial transfers.

12/12/2013 Status:
Updated the documentation on the "Manuals" page again. Added link to "clio.py" software (thank you, Bernd Grubert) for serial transfers.

12/06/2013 Status:
Updated the documentation on the "Manuals" page to reflect the latest software. Also added links to documentation for some other images (thank you, 'Angel Martin) on the "Other Docs" page.

12/05/2013 Status:
Two of those "spoken for" V4 boards are now available to anyone who wants them. I also have one V3 board and at least one V2 board. The difference between V3 and V4 is only relevant if you plan to do a direct 41CL-to-41CL serial transfer, or if you plan to solder a time module to the connection points on the top of the V4 board. All of my personal machines use V3 boards.

12/04/2013 Status:
All of the current batch are theoretically "spoken for" but I need to verify that. I'll still accept orders, though, for when I do another batch.

11/29/2013 Status:
Sent out the 41CL Extreme Functions for beta testing today. Only a couple of boards remaining from the latest batch.

10/22/2013 Status:
Preliminary spec for new 41CL Extreme Functions.

10/09/2013 Status:
Boards are all programmed and ready to go. Over half of this build has already shipped. I still need to make some more serial connectors though.

One more function to write for the new Extra Functions version. Yes, it's the most complicated one, of course.

In the process of working on this last function, I discovered that I have been misusing one of the mainframe subroutines. So the existing YPEEK function may behave strangely if a printer is present. I don't have a good enough handle on how the XAVIEW subroutine actually works to say more than that right now.

09/21/2013 Status:
Boards are back. Started programming the logic, connecting the piezo, and updating the Flash.

Still working on new Extra Functions. Two more functions to go (but they're the most complicated.) I really should update the documentation so that users can review it.

09/21/2013 Status:
Boards are on their way back from the assembly house in Colorado.

All of the new Extra Functions are done except for the most complicated one: the new versions of the PLUG functions. Argh.

09/16/2013 Status:
The latest batch is at the pick-and-place machine. On schedule.

I've been working on enhancing the 41CL Extra Functions, hoping to use dynamic paging to switch in big code blocks to Page 4 for execution. Incredibly, it seems to be working! In parallel, I need to write the spec for the new version, for user review.

09/03/2013 Status:
The latest batch is out for fab. Only 25 boards this time. This revision adds a connection between the fpga and the serial driver, so that software can force the serial driver on. This will make CL-CL transfers possible, as long as at least one of the CLs has this ability. I also added solder pads to the top of the board for the 41C bus signals. This will make it easy to connect a time module clone.

08/16/2013 Status:
Well, the cost of the components only went up by 2% overall, even though the FPGA went up by 8% and the static RAM went up by 19%. So I guess the rule is that cheap stuff gets cheaper and expensive stuff gets more expensive.

08/15/2013 Status:
The quote for assembly of another batch of boards is 30% higher per board than the last batch. Ouch.

07/01/2013 Status:
I have added a link to a .zip file with all of the Verilog source files on the "Hardware" page. This should guarantee that the design will survive me. You may or may not like my Verilog coding style, but this is what works for me. I am happy to answer questions and listen to suggestions, but make no promises about responding if the required bandwidth becomes excessive.

06/29/2013 Status:
So, while looking at the Verilog code to figure out a way to force the RS232 driver on I finally realized why the SERINI doesn't set the baud rate to 1200 like it's supposed to. I properly initialized the baud rate generator with the right value, but forgot to initialize the reload value with the right value. Rookie mistake. But I don't think I want to mess around with the FPGA programming just for this.

06/23/2013 Status:
All of the boards from the last production batch are spoken for. I'll start a waiting list for any future orders.

06/19/2013 Status:
All but one of the boards from the last production batch are spoken for. Also, I still have one V2 board. I'll start a waiting list for any future orders.

05/11/2013 Status:
The 41CL manual has been updated, incorporating the various application notes that have been generated in the past. I also cleaned up the formatting and reorganized the chapters to make it look more "professional".

03/20/2013 Status:
In case anyone is interested, Circuit Cellar magazine interviewed me for their 25th Anniversary issue, available at the Circuit Cellar Webshop. I wrote about the 41CL project in the October 2010 issue of the magazine.

03/08/2013 Status:
Okay, the keycode test in the service module now passes on my machine. 2-key rollover works as it should.

03/07/2013 Status:
I think that I have a solution to the 2-key rollover issue (at least it works in the simulation). Since this means an update to the FPGA programming I may also add banking for Page 4 at the same time.

The routines for dynamic paging fit into space available in the X-Functions image. If you are interested, the source code is available on the "Software" page. Comments are welcome.

02/26/2013 Status:
Added a release note about the 2-key rollover.

I've started working on some software that will implement dynamic paging of memory. This will allow software to switch in pages of code during a program to provide more code space (or common subroutines) as necessary for a function. This will allow me to add much more complexity to the 41CL Extra Functions if I need to. I am also thinking about implementing a "CAT 7" function that will catalog the current MMU programming, much like 'Angel does with his MMUCAT function.

01/24/2013 Status:
New manual and 41CL Extra Functions -4C posted to site.

01/24/2013 Status:
Arrrgh... I just found out (thank you 'Angel) that one of the images is improperly placed in Flash in the V3 boards. I have created a procedure to repair the problem, located here.

I have also been notified (thank you Sylvain) that the PEN and LORG functions in the Plotter module don't seem to work correctly. I don't have a way to test this myself, so I'll have to wait for further word from users.

YFNZ-4C (to fix the last "hidden flag" problem) should be ready shortly.

01/09/2013 Status:
I have just been informed that my fix for the "hidden flag" problem does not work when the calculator shuts off automatically after the ~10 minute time-out. I didn't think about this case when I was crafting the fix, obviously. This is probably going to be a royal pain to fix, but I'll keep you informed here.

01/08/2013 Status:
Updated the 41CL Calculator Manual to fix a number of typos.

12/25/2012 Status:
Updated the 41CL Calculator Manual to include YCRC results.

12/13/2012 Status:
Updated the 41CL Calculator Manual with some new images. Also updated the Image Identifier table with some new mnemonics. Any future orders will ship with these pre-installed.

10/11/2012 Status:
YFNZ-4B and YFNP-1B are available on the "software" page.

10/05/2012 Status:
I think I have a fix for the "hidden flag problem". The technique will also make it so that the current Turbo state is saved during Deep Sleep (when the calculator is turned off.) This means no more patching YFNS if you want the calculator in a specific Turbo mode at turn-on. The changes will be in a new YFNZ-4B and YFNP-1B, to be posted here as soon as I have verified proper operation.

09/28/2012 Status:
I have just been informed that the 41CL does not properly preserve a trio of internal flags when the calculator is turned off. These flags are stored in the upper bits of the ST register in the CPU. I had erroneously thought that all status information was mirrored in memory during deep sleep. The flags are: The flag that signals that the program at the program pointer is PRIVATE, the flag that signals that the program at the program pointer is in ROM, and the Stack Lift Enabled flag. Saving these flags in hardware is probably not possible, given that they would have to be moved to the CPLD portion of the design, so I am currently looking into a software way to save/restore the flags during deep sleep. Since this is the first I have heard of this issue, I assume that it doesn't affect most users. I will keep everyone updated here as I work through the issue.

09/14/2012 Status:
I have 15 boards ready to ship. The final 24 boards need to be programmed and have the piezo buzzer soldered to the board. I also need to make the last batch of serial connectors. I still haven't decided whether it's worth it to build time module daughter boards.

09/05/2012 Status:
Added a document about automatically enabling Turbo mode in the "Other Docs" section. Also updated the module mnemonic matrix with the "4SMT" (library-4 Sandmath) mnemonic. I'll add this image to the current run of boards.

08/11/2012 Status:
Batch is back from assembly. I plan to start programming/testing this week. YFNS-4A and YFNP-1A officially released.

07/26/2012 Status:
Final (really) write-up about the Image Database released on the "Other Docs" page. Now I need to generate a document with all of the YCRC check values for the Flash contents and update the documentation with any new image mnemonics.

07/11/2012 Status:
Final write-up about the Image Database released on the "Other Docs" page. YFNP-1A (41CL Extra Functions Plus) is ready for Alpha test. Send me an email if you would like to get a copy. Source code and a .ROM image are available.

06/30/2012 Status:
Added a write-up about the Image Database to the "Other Docs" page.

06/25/2012 Status:
Added the POWERCL documentation (thanks 'Angel) to the "Other Docs" page.

Still pondering whether or not to do another build...

06/12/2012 Status:
All 50 boards have shipped or been spoken for.

I'll be adding a section to the manual about how the Image Database works shortly. This will make it easy for users to add their own mnemonics. I'll still keep the "official" list for newly-released images, so that new users will have a known starting point for the database.

06/07/2012 Status:
So far 44 boards have shipped or been spoken for. Perhaps the market for 41CL calculators is now saturated, so I'm not sure about doing another batch.

I received a development board for the new Lattice iCE40 FPGA series, so I'll try to load the Timer chip clone into it to see if it fits (and works). If the design fits into one of these parts it might be possible to squeeze a Time Module clone into a module housing, but I don't know if I really want to go in that direction, because it means destroying what is probably a perfectly fine module just for the housing.

05/18/2012 Status:
Release notes updated. 34 boards shipped so far. The Time Module clone is ready to fab, but I suspect that it is going to be too expensive using Xilinx CPLDs. The new Lattice parts look very attractive, but when will they really be available?

05/11/2012 Status:
The 4 reworked boards are back from the assembly house. They replaced the power-supply controller (just in case it was damaged by the shorted inductor) and the inductor. Need to test them tomorrow.

Caught up on orders for this batch: 30 shipped. Still need to find homes for 20 more.

If you're interested, this is where the 41CL boards have found homes.

05/02/2012 Status:
So I bought an IR thermometer to see where the high current was flowing in the 4 failing boards. Scanning the board revealed just one hot spot: the inductor in the switching power supply. Hmmm... everything looks okay, so let's compare this board with a good one. Incredibly, the inductor on the failing boards is placed rotated by 90 degrees! The 4 boards go back to the assembly house for rework tomorrow.

05/01/2012 Status:
I sent 41 notices out that boards were available. 23 people responded with orders for 27 boards. 3 people said no thanks and 16 didn't repond. That's a slightly lower response rate than in the past. Ordered more Port covers and serial cables just in case more orders come in.

04/27/2012 Status:
46 boards ready to ship. 4 boards failed because of excessive current. I need to investigate this before I order another batch.

04/24/2012 Status:
First board from this batch seems to work fine. Piezo buzzers soldered. Now I need to program all of the FPGAs.

Cleaned up the "Release Notes" page on the website.

04/16/2012 Status:
PC boards are back from the assembly house. Will program the hardware and solder the piezo buzzer on one board to start the verification tomorrow. Assuming that everything works, I'll start on the remainder of the batch and start notifying people on the waiting list.

04/11/2012 Status:
Spent the day assembling 50 serial connectors. Now I can't straighten out my back or focus my eyes beyond twelve inches.

04/05/2012 Status:
I ordered 50 FPGAs from DigiKey, and the anti-static bag said that there were 50 pieces inside. But when it was opened at the assembly house there were only 49 inside. So the job went on hold for the three days it took me to get them one more piece.

03/22/2012 Status:
Spent all day yesterday programming the Flash memories for another batch. It sure would be nice to have a gang programmer instead of having to do it one-at-a-time. Parts shipped to the fab house today.

03/19/2012 Status:
There is an error in the first release of the Image Database. The entry for the MADV mnemonic is incorrect. The correct value for this mnemonic should be 40F8 (not 207C). The IMDB files on this website have been updated.

03/10/2012 Status:
I just discovered that the YFWR function does not prevent writing to the OS area! So be warned that you should NEVER try to write to the OS area of the Flash, or you will brick your calculator like I just did.

This warning applies to ALL versions of YFNZ prior to -3B.

03/09/2012 Status:
Oops. Not enough testing. Posted fixed yfns-3a to site.

03/08/2012 Status:
Posted yfns-3a to site.

03/02/2012 Status:
The FPGA programming change to support banks in Pages 6 & 7 fits in the device. Just need to verify that it works correctly.

03/01/2012 Status:
The FPGA programming change for the HEPAX DISASM issue has been verified. The FPGA programming change to fix the OS mapping function has been verified.

02/27/2012 Status:
Preliminary schematic for Timer Module replacement completed and posted.

02/20/2012 Status:
V3 Flash image built. Components ordered.

02/19/2012 Status:
Updated manual, covering YFNS-3A and V3 hardware, posted to site. This time around I'm not going to notify people until I actually have boards ready to ship. The stress of trying to debug boards after people had already paid was too much.

02/16/2012 Status:
Just to be clear, the Version 3 hardware does not include the timer functionality. It does double the size of both the Flash and the RAM.

I am going to try to design a separate time module replacement board. The design rules for the BGA packages are a LOT tighter than what I used on the 41CL boards, and I don't want to have to fabricate the entire 41CL board with those tighter ($$$) design rules. There isn't room on the 41CL board for all of the packages required for the timer anyway.

02/15/2012 Status:
41CL Version 3 PC board released for fabrication.

The time chip design requires three CPLDs, each in an 8mm x 8mm BGA package. A pair of XC2C256 devices and a single XC2C128. One "256" device is 95% utilized, containing channel A. The other "256" device is 89% utilized, and contains channel B. The "128" device contains the bus interface and is 75% utilized. I would use a "512" device instead of the pair of "256" devices, except that the package options are all physically too large. This is a full implementation of the HP spec except for the start/stop inputs, which are not used in the Time module. The interface CPLD can also be used wth an implementation that uses a microcontroller for the timer functionality.

02/14/2012 Status:
The version 3 board design is complete and checked. Hopefully this will be the final version. Since there are about 35 people on the waiting list, I'll probably start another batch shortly after I get the bare PC boards back.

02/02/2012 Status:
Added updated manual for YFNS-3A to the website.

01/31/2012 Status:
YFNZ-3A is almost ready to release to testing. Cleans up the error handling, removes the need for patching when loading via other than the serial port, uses the image database for the PLUG functions, automatically copies at 50x turbo, outputs a status message during long operations, etc. Will be updating the manual with the changes next. Still need to check the new board layout before sending it out for fab.

01/20/2012 Status:
The problem with the MAPEN function is hardware-related. The issue with the HEPAX DISASM function can be repaired with a simple patch. See the new "Release Notes" page.

01/14/2012 Status:
User feedback says the accuracy factor feature in the timer chip is important. That may mean no timer chip clone in a CPLD. C'est la vie.

01/12/2012 Status:
Oops, the timer chip actually requires 506 flip-flops. Trimming the accuracy factor logic, which I suspect that not everyone uses (I know that I haven't used it) means it should fit in the XC2C512, but there is no way this device will fit on the 41CL board. An XC2C384 might fit, if it replaced the current CPLD, because it comes in a TQFP144 package. But that would limit me to about 320 flip-flops. That limit would compromise the functionality.

On a more positive note, I am just about done with the circuit board modifications.

01/07/2012 Status:
The timer chip requires 326 flip-flops, which means that it MIGHT fit in a CPLD. But I don't see a way to include the functionality on the 41CL board itself. There just isn't enough room on the board for another package, especially one that is 17mm square (this is the smallest package for the biggest CPLD). So don't everyone get your hopes up.

Theoretically I could just replace the current CPLD, but the new package is BGA, which is going to mean more layers on the PC board, and my board layout tools only support up to the four layers that I currently use. Upgrading the board layout tools is expensive, so that is not likely to happen.

01/06/2012 Status:
Clone of the timer chip seems to work in the simulation. It was a nice challenge to guarantee that time is kept properly independent of deep sleep/light sleep/run state. It's interesting that the HP spec for the chip is 30 pages, but the Verilog code for the design only requires 12 pages. Now I can get back to revising the printed circuit board layout and then think about starting another batch.

12/31/2011 Status:
Almost done with a clone of timer chip. Still need to finish board layout modifications and decide whether or not to order a new board revision. I should probably start thinking about modifying YFNS to use the Image Database.

12/24/2011 Status:
48 boards have shipped. I have one board that can be soldered in place rather than using the press-fit connector. I soldered this board to my test calculator for debugging, so the connector land pattern is pre-tinned, which makes the surface uneven and unsuitable for use with the press-fit connector. Contact me if you are interested.

Started modifying the PC board layout to add a dedicated pull-down resistor so that I don't need to manually solder a jumper on the board. Considering other modifications at the same time:

1. Route two extra address lines to the Flash memory to allow for a 2x or 4x larger Flash?

2. Route an extra address line to the RAM memory to allow for 2x larger RAM?

3. Add three extra connections between the FPGA and the CPLD, just in case? This would allow one more status bit to be stored in the CPLD, which would retain the status while the calculator is off.

12/13/2011 Status:
Total of 42 boards have shipped. Slow going now because I have to notify people two or three at a time to make sure that I don't over-commit. Still seeing that one out of three people don't even bother to respond one way or the other.

Now I need to decide whether to do a build of 25 using the remaining bare boards or go ahead and revise the board to avoid soldering the jumper (hoping that I can sell more than 25).

12/11/2011 Status:
Started notifying the next people on the waiting list. There are 11 boards remaining.

The December issue of Circuit Cellar magazine has an interview of me if anyone is interested in learning what makes an IC designer tick.

12/07/2011 Status:
Caught up with orders, with a total of 33 boards shipped. 14 people didn't respond with an order, so they lost their place and the next people on the list will be notified shortly.

11/30/2011 Status:
10 boards shipped today. Invoices are out for 3 more, awaiting payment.

11/29/2011 Status:
11 boards shipped today. I hope to be able to catch up tomorrow. As with the beta boards, only about two-thirds of the people who said they were interested actually respond when I send them a link to the order form. I'll probably offer the unclaimed boards to the next people on the waiting list at the start of next week.

11/28/2011 Status:
I can only solder about 7-9 jumpers before my hand gets too shaky to be successful. So 7 boards shipped Saturday, and 9 will ship tomorrow. Plan is for another 8 or 9 on Wednesday. Then I'll be caught up.

11/25/2011 Status:
Repairing the boards requires just a single jumper. I plan to start shipping tomorrow.

11/23/2011 Status:
A single pull-down on PWO_HI should be sufficient, since this is the master reset for everything on the HP-41 bus. I was originally targeting the clocks because those signals go through vias, which are easy to solder to. But PWO_HI should be the correct fix. It's just a little harder to solder to. Will verify tomorrow.

11/22/2011 Status:
Resistors arrived today. Reprogrammed the CPLD and FPGA for half of the batch. Still need more testing on the fix, but looks good so far. I probably just jinxed everything by posting that.

11/21/2011 Status:
It may require three resistors for a guaranteed fix. Pull-downs just on PH1_HI and PH2_HI make the board start up properly 99% of the time. But I may also need one on PWO_HI for the final 1% case (where the calc has been off for a long time and the start-up delay is slightly longer). It will always start with a second press of "ON", but I haven't yet checked it with the Time module installed. Resistors should arrive tomorrow or Wednesday.

Lessons learned:
1. Just because it worked once doesn't mean it will work again.
2. Low-power design is tricky. (Duh. I already knew that.)
3. You can't fix everything with programmable logic.
4. It's good to have signals go through vias, for soldering patches.
5. Always bring unused CPLD and FPGA pins to vias too, for potential future use.
6. Always provide extra connections between the powered (CPLD) logic and unpowered (FPGA) logic.
7. The right tools (e.g. a mixed-signal sampling scope) make debugging easier.
8. Never assume. Completely test one board before programming the rest of them. (Duh. I already knew that too. Shortcuts can be fatal.)

11/20/2011 Status:
CMOS chips have an "activation" voltage, related to the transistor threshold voltages, below which nothing works. This batch of FPGAs has an activation voltage higher than that of the level shifters used to create the 41 bus signals. As a result the level shifters start operating prior to the FPGA outputs being valid. In my defense, I don't have a mixed-signal sampling oscilloscope, which would have made the problem obvious.

The addition of two pull-down resistors should solve the problem. The pull-down resistors in the FPGA don't help because they really aren't resistors, so they don't start "working" until the FPGA activation voltage is reached.

11/18/2011 Status:
Using an output from the CPLD to disable the PWO output from the FPGA during deep sleep doesn't help. That means that the problem is most likely occurring during the time before the power supplies are stable, while the FPGA outputs are supposedly "floating". Time to try the programmable pull-downs on the FPGA pins.

11/17/2011 Status:
The logic in the CPLD assumed that PWO and DPWO would not be active while the board was powering up (which is the correct behavior). I have modified the CPLD logic so that the state of these two signals is ignored during the power-up time. Now I need to try to modify the FPGA logic to somehow make the PWO output stay Low while the reset signal is active (like it's already supposed to do).

11/16/2011 Status:
This is incredibly frustrating. If I have to scrap this batch I won't be able to afford to build another.

The thing works fine except when waking up from deep sleep. PWO goes High for no reason, despite the fact that the reset signal is active, supposedly holding the flip-flops static! This throws off everything, because the entire system is synced to this edge.

11/15/2011 Status:
It would be nice if the effing FPGA would operate properly. During power-up the reset input to the FPGA is held active for several milliseconds after the power is stable. But this batch of FPGAs appears to completely ignore that fact, and signals that come from flip-flop outputs (supposedly reset) are High! WTF? This messes up everything, because the logic assumes that a couple of these signals really will be Low during reset.

11/10/2011 Status:
The start-up of a beta board is a thing of beauty. From zero to full speed with nary a glitch. With this batch the start-up is a complete mess... start-stop multiple times. Weird ISA bus timing, PWO toggling... No wonder there's a problem.

11/09/2011 Status:
The boards are failing the final test. WTF? I guess that's what happens when you accept orders before final test. I should know better.

UPDATE... seems to be related to fast OFF-ON issue noticed with the beta boards. Time to get to the root cause. Some kind of race?

11/08/2011 Status:
Flash update is taking 25 minutes per board because of the solution books. Grrr....

11/05/2011 Status:
FPGA programmed on all boards.

11/03/2011 Status:
CPLD programmed on all boards. FPGA programming next. Flash update image ready (unless there are more solution books).

11/01/2011 Status:
Piezo buzzers and power connections done on all boards. CPLD programming is next.

10/29/2011 Status:
Serial connectors done. Port covers modified. Piezo buzzers and power connections are next.

10/24/2011 Status:
First batch of 50 is back. Working on making the serial connectors. Need to also mount the piezo buzzers and program the CPLD and FPGA on each board, update the Flash, plus a quick final test. Each serial connector takes about 10 minutes to make. Then another 10 minutes with the Dremel tool (using three different heads) to modify the Port cover. Mounting the piezo buzzer and power wires for programming is about 3 minutes and CPLD/FPGA programming takes 5 or 6 minutes. Updating the Flash takes about 11 minutes. Multiply by 50 boards. This is why it's taking so long.

09/21/2011 Status:
First batch of 50 out for assembly. Time to solder some serial connectors...

09/17/2011 Status:
Added documentation for Production version. Parts for the first batch of 50 have been ordered. We expect to have boards available early in October.

08/06/2011 Status:
Added document describing hardware programming.

08/03/2011 Status:
Fixed the .rom files here so that no patch is required for YFERASE and YSEC when running in Turbo mode.

Simulated fast OFF-ON sequence. All waveforms look fine. Must be something undocumented in the timer chip?

07/22/2011 Status:
Beta status document updated with yfns .rom file patches. Revised YFNS to revision 1E. Added files section to website.

07/16/2011 Status:
Second report of a problem with YFERASE. Until further notice I recommend not using the flash functions.

07/15/2011 Status:
WROM instruction fix verified. Compiled logic fits in FPGA. Need to verify on a board. Flash update image built.

07/09/2011 Status:
Revised YFNS to revision 1C. Will try FPGA update to fix WROM instruction later today.

06/16/2011 Status:
Updated 41CL Manual to include OS register usage.

06/15/2011 Status:
The sample labels arrived. Here's what my finished 41CL looks like.

06/14/2011 Status:
The last two boards shipped today. Thank you to all of those who took a chance and ordered one. Here is where the 21 boards found homes: Australia (x2), Canada, Canary Islands, England, Finland, France, Germany, Italy (x2), Norway (x2), Singapore, Switzerland (x3) and the USA (x5). (Plus the one I kept for myself, the development board, the two that got smoked during testing, and the two Alpha boards.)

06/13/2011 Status:
Three more boards shipped today, for a total of nineteen. Modified my last three Port covers. Hoping to find homes for the last two boards. Updated manual with part numbers for do-it-yourself serial connector. Added final schematic to website for reference.

06/11/2011 Status:
One more board shipped today. First user feedback is positive. Yeah!

06/10/2011 Status:
Three more boards shipped today. Several have already arrived at their final destinations.

06/08/2011 Status:
Three more boards shipped today. Eight remaining to go. Created layout for 41CL label samples. Feedback welcome.

06/06/2011 Status:
Nine boards shipped today. By not responding with an order form, five people lost their spot on the "top twenty" list today.

06/03/2011 Status:
Ten invoices sent. Will start shipping Monday! Finally, the end of the project is in sight.

06/02/2011 Status:
Ten port covers modified for serial connectors. Should finally be able to put away the oscilloscope, logic analyzer, power supply, programming cables and soldering iron. :-)

06/01/2011 Status:
Flash updated on all boards (65minutes/board x 22 boards). Twenty-five serial connectors soldered. Still need to modify Port covers. Trying to figure out international shipping (a royal pain).

05/26/2011 Status:
CPLDs programmed on all the boards. Lost one board due to "bad id" returned from CPLD during programming. Another $200 up in smoke. FPGAs programmed on all the boards.

05/19/2011 Status:
The first thing I always asked a customer with a problem was "Did you read the datasheet?" I swear I read the datasheet, but that was a couple of years ago. Duh. I forgot that the JTAG reset signal was active-low. So now I can update the Flash memory with the final software. Sent the order form to the lucky 20 people who were first in line!

05/17/2011 Status:
Still can't get the JTAG programmer to talk to the JTAG chain on the board. Either there is something magic involved or I am overlooking something very basic.

05/05/2011 Status:
New flash images are ready and the JTAG configuration files are all set up. Too bad I can't get the effing JTAG programmer to talk to the JTAG chain on the board.

04/27/2011 Status:
The Flash functions (Erase and Write) in the 41CL Extra Functions don't work, because of a stupid coding mistake. Sorry, I'm really a hardware guy. Now I have to find a way to make the corrections fit. On the bright side, this should be the last of the changes to this code, as everything else seems to work okay.

04/22/2011 Status:
41CL manual updated with changes to be applied before release. Still need to try out revised Y-Functions in emulator. Might be able to try JTAG reprogramming of Flash tomorrow.

04/21/2011 Status:
Piezo buzzer and power wires for programming soldered to all 23 PC boards and I only dropped the soldering iron on my leg once. I'm sure that I'm working for Bangladesh wages on this project.

04/19/2011 Status:
New Flash image built except for revised Y-functions. Six new ROM images and six updated ROM images. Need to finalize Y-functions and then try to reprogram the Flash via JTAG. Cross your fingers.

04/18/2011 Status:
YGET (serial input) now works properly. Still not sure how to test YIMP (serial block input). Hardware issue was improper handling of register address in some cases. Logic got broken when I modified the logic to make register reads and writes run at turbo speed, rather than always at 1x. Oops. JTAG programmer should arrive tomorrow. Working on generating the configuration files necessary to try to program the flash via JTAG. Planning on modifying Y-Functions to include a couple of new images.

04/13/2011 Status:
YGET still doesn't work correctly. More investigating. Buffer functions work, but have to restrict to physical addresses. Also have to restrict export and import to physical addresses. Incredibly, something has broken User mode. More investigating. Tired of keying in patches, so I've ordered a JTAG programmer for the Flash memory.

04/11/2011 Status:
Found the issue with the YGET (serial read) function, and it's messy to fix. Requires 16 more locations be patched, so I'm afraid I'll have to do the patches myself for the boards and write the code to an open slot in the Flash. I wish JTAG programmers weren't so expensive, because with that I could just reprogram the Flash in one shot and even add new images before release. Oh well.

04/09/2011 Status:
PEEKing and POKEing confirms that the serial receive hardware is working correctly (yea!) so now I need to figure out what's wrong with the YGET (serial read) function. I still don't know how to test the YIMP (serial block import) function. Need to expand the manual with the various things I've noticed, like YGET doesn't pop the fifo in the case of an overflow, so you need to do SERINI to clear an overflow.

04/08/2011 Status:
Duh. The RS232 chip automatically shuts off with no valid level on the RX input. Serial port transmitter works. YGET function (serial receive) always returns indicating overflow for some reason. Investigating.

04/06/2011 Status:
Updated NEWT manual for I/O Port operation. Serial functions need twelve locations patched. Perhaps too many? Okay, serial port sends out of the fpga... but doesn't make it through the rs232 driver? Transmitter sends two stop bits, which is okay (something I forgot, obviously). Baud rate is correct, but there are gaps between chars when running 1x, which was expected.

04/05/2011 Status:
Version 2 boards draw only 110uA in deep sleep. The changes made from the initial version to reduce deep sleep current draw worked. Found another bug in the serial functions. More patches to come.

04/04/2011 Status:
Updated the 41CL manual with a section on patching code. Updated NEWT microprocessor manual for start-up delay.

04/02/2011 Status:
Well, each of the serial functions have some kind of problem. That's the problem with using an instruction simulator to check code. Now I could correct most of them by changing the hardware, but even if I did that, there would still be at least one patch required. Trying to decide which way to go... leaning towards just issuing a set of patches, but first I need to verify the hardware.

04/01/2011 Status:
Version 2 boards now appear to be working and stable. I changed the voltage regulators (for lower quiescent current) on version 2, and they start up more slowly. So the start-up delay in the CPLD was releasing reset before the FPGA power was really stable, which led to the PWO logic not always working correctly.

Since I wasn't sure that this was the only problem, I also modified the PWO logic to eliminate a gated clock. This means a little bit more power, but the logic is much more tolerant of timing issues. It also helps the synthesis and routing, as the tools seem to have a harder time dealing with multiple clock domains.

So now I just need to go through some final checks (mainly the serial port) before I start programming the boards for general release.

03/28/2011 Status:
Issue appears to be related to the timing of PWO and/or DPWO on start-up. The fail cases have these signals rising with the first edge of PH1, which isn't how the logic is supposed to work. And it means that the display driver is out of sync with the CPU, which explains the garbage display.

03/25/2011 Status:
Second board isn't working. Time for debug. Had to add some circuitry to account for potential skew on the reset input. Also corrected a couple of flip-flops that were not being initialized by reset. These were _probably_ the source of the start-up flakeyness, because they could lead to the turbo control getting confused.

03/22/2011 Status:
Went through the entire design with a fine-toothed comb. Amazing how many little things ("what was I thinking?") one can find going back like this. Everything should be solid now.

But then the design tools decided to stop working (aborting in the middle of a step). After a week of hair-pulling, I started a new project from scratch in a new directory. It now compiles, so now we'll see if it works or not. Stay tuned...

UPDATE... the new project failed to import the pin assignment list properly (and I didn't check it) so the development board is toast. I hope the display driver on the calculator main board wasn't affected. Grrr... $200 up in smoke.

03/09/2011 Status:
Several of the changes made during debugging did not properly account for clock-domain crossing. Working on fixing these. Want the boards bullet-proof before release, so be patient.

03/05/2011 Status:
Problem occurs less often with logic recompile. WTF.

03/04/2011 Status:
The "flakeyness" that I saw in the test calculator is something in the FPGA. About 20% of the time turning the machine on will cause the main state machine to go awry. This never happened in the rev 0 boards. Now, the code did change, to support internal code for Page 5, but the code ran fine on a rev 0 board. Time for some serious debugging.

02/22/2011 Status:
Something flakey with a Rev 1 board in my test calculator. The Xilinx programmer fried the mouse port on my computer. Notified of an error in one of the ROM images. Time to write a "How to Patch Code" chapter for the manual. Not a good day.

02/16/2011 Status:
Assembled boards are back, ready for final debug. If you have already asked me to put your name on the "interested" list, I'll be contacting you shortly. All of the boards are spoken for. Remember that these should be considered "beta test" units, so if you really don't want such a unit, let me know so that I can offer it to someone else.

02/10/2011 Status:
41CL Calculator manual updated with photos.

01/26/2011 Status:
Finally! Out for assembly.

01/23/2011 Status:
Final version of 41CL Calculator Y-Functions source code released.

01/22/2011 Status:
All parts except the Flash memory kitted for assembly. Manual updated describing how to use Forth image. Final flash image is built, ready for programming.

01/14/2011 Status:
Quotes for assembly received. 41CL manual released.

01/04/2011 Status:
Bare PCBs received. One last update for Flash received.

12/18/2010 Status:
Service Module reports "CPU OK".

12/17/2010 Status:
Service Module reports "CPU BAD". Problem is with decimal mode when inputs are greater than 9. Investigating.

12/15/2010 Status:
First production PC boards ordered.

12/13/2010 Status:
HEPAX HEPDIR command works now that WROM instruction is fixed.

12/08/2010 Status:
WROM instruction is AFU. Perhaps that's why HEPAX doesn't work.

11/29/2010 Status:
Tech manual updated. Download what is close to the final version.

HEPAX image doesn't work properly. Don't know why yet.

Board design finalized. Board #2 has been in a calculator body, running off of batteries, for two weeks.

11/11/2010 Status:
82160A HP-IL Module seems to work. Since I don't have any HP-IL peripherals the testing was rather cursory.

Going through the board design to try to reduce current drain.

11/05/2010 Status:
82153A Wand appears fully functional!
82242A IR Module appears fully functional!

Turns out that the IR module expects the CPU to sample the FI bus during the second clock in a nibble time. (Undocumented)

And the Wand screech and failure during WNDTST was due to an error in the CLRST instruction.

11/03/2010 Status:
Oops. Turns out that "WNDTST" only reports the correct data for the first byte. Second byte is AFU in display, but correct in the register. This one is going to be hard to find, given that I can't use V41 to step through code. Hmm...

11/01/2010 Status:
82143A Printer appears fully functional.
82104A Card Reader appears fully functional.
82182A Time Module appears fully functional.
82153A Wand appears fully functional, but piezo element screeches during operation. Need to investigate.
82242A IR Printer Module still reports "BAD" with TESTP.

10/28/2010 Status:
82143A Printer mostly works. "Print" button on printer does not print.
82242A IR Module prints one line, but then errors. TESTP reports "BAD".
82160A HP-IL Module not tested yet.
82153A Wand doesn't start with button press. "WNDTST" mostly
works, but causes piezo element to screech instead of beep.
82104A Card Reader doesn't start up when card is inserted, but does
"VER" on cards, and does write cards.
Time Module doesn't display continuous time with "SHIFT"-"ON".

All of this points to a problem with peripherals pulling the ISA line
High to start the calculator.

May also be issue with instructions executed during SELPRF?

10/21/2010 Status:
The flag input is active-Low, which I missed in the HP specs. I am also sampling it during the wrong bit time... This requires a circuit board change as well as Verilog. The HP spec also says that the CPU precharges this signal, which I have no way of doing as it stands right now. Investigating.

10/11/2010 Status:
82143A Printer catalogs properly, but always says "printer off".
82242A IR Module hangs the machine on start-up.
82160A HP-IL Module catalogs properly, and seems to execute, but
I have no HP-IL peripherals to verify this.
82153A Wand makes the calc start-up wierd, with high-pitched screech.
Catalogs properly, but doesn't seem to work. Also, doesn't start
calculator with press of button on wand.

All of this can probably be attributed to something wrong with the SELPRF instruction and/or flag input.

09/24/2010 Status:
Buy a copy of the October issue of Circuit Cellar magazine! My article about the design is there. Found a source for the CD40109 (thanks Gene), so I'll be able to do the first production run soon.

Still have lots of things to verify though, by putting board number 2 in a calculator body to verify operation with things plugged into the physical ports.

Also need to build the Flash image for the release version.

08/17/2010 Status:
Deep Sleep: 310uA, Light Sleep: 4.2mA, Run: 7.9mA
Register read timing change verified.
"Loop of addition" benchmark:
1x: 1055
2x: 1913
5x: 4153
10x: 6538
20x: 9179
50x: 12022

08/14/2010 Status:
Light Sleep current drain reduced by disabling clock. Register read timing changed to improve Turbo mode performance. Need to verify. First production components ordered.

08/06/2010 Status:
Investigating if it's possible to change the design to do register writes at turbo speed, which will improve turbo performance. Also investigating ways to improve Light Sleep current drain.

08/02/2010 Status:
Found the light sleep current drain - floating data bus. Deep Sleep: 330uA; Light Sleep: 6mA; Run: 7.7mA (no turbo) Almost ready to order first production batch!

07/29/2010 Status:
Light Sleep current isn't from FPGA after all. Still looking. Software for PEEK and POKE for I/O do bytes. Need to modify to do words.

07/23/2010 Status:
PLUGx only works correctly with 4K modules. Software issue. Had to delete 4-byte transmit buffer to make room for changes.

07/22/2010 Status:
User mode operation fixed. Problem was with c=regn instruction. PLUG3 issue is a software bug. Updated spec posted to site.

07/20/2010 Status:
User mode doesn't work. Machine hung when I tried to PLUG the Real Estate module into Port 3.

07/19/2010 Status:
Turbo mode works!!

07/16/2010 Status:
The MMU seems to work. Module images can be plugged into ports and unplugged from ports! Turbo mode does not work. Still no resolution to the power issue, but problem when eliminating continuous reset may be due to dpwo signalling with display drivers.

07/13/2010 Status:
POKE works... just not with an on-chip peripheral address. Grr... Eliminating continuous Reset during Light Sleep works in sim but not in the FPGA. More grr...

07/10/2010 Status:
90% sure that Light Sleep power issue must be due to FPGA being held in Reset during this time. Hmm... Added option to enable/disable MMU via peripheral write. Necessary because of error in the code in Flash. Will test next. Verified that POKE works. Looks like block copy works. Fixed Bank Select and Turbo state so they're preserved in Light Sleep.

07/09/2010 Status:
Still haven't found the light sleep power issue. Corrected an issue with updating register address and PFAD Corrected the WCMD instruction write cases, so now POKE works. Corrected the WCMD instruction read cases, so now PEEK works. The bank switch bits are not preserved during light sleep. Investigating. Still haven't changed the clock to stop during light sleep. Getting POKE to work means that I can now test the Turbo modes and program the MMU to verify the PLUG and UNPLUG commands!

07/07/2010 Status:
Model of display chip working. Makes simulation easier. Also means that I can build an interface to a different display. LEDs?

07/04/2010 Status:
Oops, the MMU was being disabled by light sleep. That's fixed. Also the data bus and the isa bus were both being driven during light sleep. Is that the source of the current drain during light sleep? We'll see. Need to disable the clock inside the FPGA during light sleep. That will save 5-10mA.

07/03/2010 Status:
The flag output wasn't initialized during light sleep or deep sleep. Since the Actel flip-flops like to power-up holding a one, that meant the output was always High until a TONE or BEEP. Not sure how that would affect the piezo buzzer. Fixed.

07/02/2010 Status:
The problem with running programs has been found. The CLRST
was clearing all 12 bits of the ST register.

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