The latest versions of the Verilog source files for our designs are here:

41CL Calculator (.zip)
Time Module clone (.zip)

The schematics for all of our board designs are here:

41CL Calculator schematic (.pdf, V5 board revision)
41CL Calculator schematic (.pdf, V4 board revision)
41CL Calculator schematic (.pdf, V3 board revision)
41CL Calculator schematic (.pdf, V2 board revision)
41C Flexible Hardware Module (V1) schematic (.pdf)
41C Flexible Hardware Module (V2) schematic (.pdf)

Board connection points are shown here:

Bus connection points (top of V4/V5 board) (.jpg)

The FPGA can be reprogrammed using the Actel FlashPro software and hardware. The CPLD can be reprogrammed using Xilinx ISE software and hardware.

FPGA programming file (.pdb) 03/12/2014 version
CPLD programming file (.jed) 05/13/2013 version

The Flash memory on the board can be programmed via JTAG. This requires a BSDL file to describe the JTAG chain configuration and a configuration file that describes the connection between the FPGA and the Flash memory.

BSDL file for the Actel device (.bsd)
Flash configuration file for the 41CL board (.topflash)

The Flash memory on the board can be reprogrammed via JTAG.
We use TopJTAG software and the JTAG-USB hardware.